1. Field of the Invention
The present invention relates to a semiconductor device of MOS structure, and more specifically to a semiconductor integrated circuit device provided with a wiring microstructure formed on gate electrodes, and a method of manufacturing the same integrated circuit device.
2. Description of the Prior Art
With the advance of higher integration of the semiconductor devices such as ICs or LSIs, higher miniaturization technique has been required more and more. In the semiconductor integrated circuit device of MOS structure widely used as memory devices, in particular, since a plurality of gate electrodes are arranged in a well, the interval distance between the gate electrodes has been narrowed more and more with the advance of the microminiaturization technique. In this case, the wiring for connecting active regions formed in a semiconductor substrate to other regions through the surface of the semiconductor substrate is usually formed in accordance with gate self-alignment contact technique (referred to as gate SAC method or structure, hereinafter), by which contact holes are formed between the gate electrodes. Conventionally, however, when the contact holes are formed in the self-alignment contact structure, in order to prevent the wiring contacting the underlayer semiconductor substrate from being shorted to the gate electrode of the MOS transistor, the upper and side portions of the gate electrode are covered with an insulating film whose etching speed is lower than that of an interlayer insulating film formed on the semiconductor substrate, so that an insulating film with a sufficient film thickness can be retained between the gate electrode and the wiring after the contact has been formed between the gate electrodes.
In this conventional method, however, when the over-etching time is prolonged to form the contact holes, since the insulating film is etched away at the upper and side portions of the gate electrodes, the margin is reduced in the manufacturing process. To overcome this problem, that is, to securely leave the insulating film, the other method has been so far proposed such that: the gate electrodes are covered with an insulating film; an insulating film and a poly-crystal silicon film are deposited all over; another insulating film is deposited and then melt for planerization (flattening) process; the insulating film on the poly-crystal silicon film is removed by such an etching method that the etching ratio of the insulating film to the poly-crystal silicon can be selected; and thereafter the poly-crystal silicon is removed. In this manufacturing method, since the interlayer insulating film contacting the semiconductor substrate can be etched so as to be fairly thinner than that of the insulating film covering the gate electrodes, without etching the insulating film covering the gate electrodes, it is possible to secure the insulating film having a sufficient thickness around the gate electrodes, even if overetched to some extent.
The above-mentioned conventional method of manufacturing the semiconductor integrated circuit will be described in further detail with reference to FIGS. 1A to 1F. In this manufacturing process, as shown in FIG. 1A, an element separating region 16 is first formed in an N-type silicon semiconductor substrate 1 in accordance with LOCOS (localized oxidation of silicon) technique. Thereafter, a P well region 21 is formed and then a gate oxide film 2 of SiO.sub.2 is formed all over the semiconductor substrate 1 by thermal oxidation, for instance. Further, a gate electrode 3 (31 and 32) of poly-crystal silicon are formed on the gate oxide film 2 and a siliside film of high melting point metal such as Mo or W is deposited on the poly-crystal of the gate electrode to reduce the resistance of the gate electrode 3. A WSi.sub.2 film 32 is formed on the poly-crystal silicon film 31. The resistance of the poly-crystal silicon film 31 is reduced by diffusing B or P ions thereinto at high concentration. The gate electrode 3 is covered with an insulating film 4 of SiO.sub.2, for instance. Successively, N-type impurities are ion-implanted into the well region 21 of the semiconductor substrate 1 to form an N-type source/drain region 22 on both sides of the gate electrode 3 in the semiconductor substrate 1.
Further, an insulating film 23 of Si.sub.3 N.sub.4 is formed on the surface of the semiconductor substrate 1 so as to cover the gate electrode 3 and the-insulating film 4 which covers the electrode 3. In addition, a poly-crystal silicon film 24 is deposited on the insulating film 23, and then another thick insulating film 8 of BPSG (boron phosphorus silicate glass) is formed on the poly-crystal silicon film 24.
Thereafter, the surface of the BPSG film 8 is melted for planerization. As shown in FIG. 1B, a photoresist 9 is formed on the BPSG film 8 except a predetermined region between the parallel arranged gate electrode 3, and a contact hole 25 is formed by opening the portion at which the BPSG film 8 is exposed in arrow direction A in accordance with anisotropic etching (e.g., RIE (reactive ion etching)), for instance. This contact hole 25 is formed relatively wide to such a degree as to extend to over the gate electrode 3. The etching speed of the planerized BPSG film 8 is about 50 times higher than that of the poly-crystal silicon 24. Therefore, even if the BPSG film 8 is opened almost completely to form the contact hole 25 in the BPSG film 8, the poly-crystal silicon film 24 under the BPSG film 8 remains as it is without being etched.
Further, as shown in FIG. 1C, the poly-crystal silicon film 24 in the contact hole 25 is removed by etching in arrow direction B to expose the insulating film 23. Then, as shown in FIG. 1D, a poly-crystal silicon 24 (for covering the gate electrode 3 and the insulating films 4 and 23) is treated oxidation at a high temperature of about 800 to 900.degree. C. to change the poly-crystal silicon film 24 to silicon oxide as a part of the BPSG film 8. Further, as shown in FIG. 1E, the insulating film 23 and the gate oxide film 2 in the contact hole 25 are removed by the anisotropic etching (e.g., RIE) in arrow direction C to expose the surface of the semiconductor substrate 1. Further, another insulating film (not shown) is formed all over the surface of the semiconductor substrate 1, this insulating film is removed by the anisotropic etching to form an insulating side wall 28 of the gate electrode 3 in the contact hole 25. In this process, as shown by arrow D in FIG. 1E, the insulating film 4 for covering the gate electrode is slightly etched off. Thereafter, as shown in FIG. 1F, a wire 10 (101 and 102) connected to the source/drain region in the semiconductor substrate 1 is formed on the contact hole 25 and the planerized BPSG film 8. The wire 10 is formed of a poly-crystal silicon film. However, the wire 10 can be formed as a multilayer film composed of the poly-crystal silicon film and the siliside film of a high melting point metal such as Wsi.sub.2. The resistance of the poly-crystal silicon film is reduced by diffusing B or P ions at high density in accordance with the ion implantation technique.
In the conventional MOS type semiconductor device as described above, the resistance of both the poly-crystal silicon film 31 for constituting the gate electrode and the poly-crystal silicon film 101 (formed as the wire) of the gate SAC structure is reduced by diffusing impurities such as B P ions at high concentration in accordance with the ion implantation. However, when the wire 10 is arranged over the gate electrode 3, since the ions enter the gate electrode 3 through the wire 10, so that the impurities increase excessively and unnecessarily in the gate electrode Further, when the conductive type of the impurities entering the gate electrode is different from that of the impurities existing in the gate electrode, since the impurity concentration is substantially reduced, it has been difficult to obtain stable gate characteristics.
Further, in the conventional method as described above, since the etching rate of the insulating film 4 for covering the gate electrode 3 is not different so much from the etching rate of the interlayer insulating films 23 and 8 deposited on the insulating film 4, when the contact hole 25 is over-etched during the contact hole opening process, the thicknesses of the insulating films 23 and 8 for covering the gate electrode 3 are reduced, with the result that the wire 10 and the gate electrode 3 are shorted to each other in the worst case. The poly-crystal silicon film 24 is employed as a stopper for preventing the above-mentioned short.
Although etching rate of the poly-crystal silicon film 24 is considerably slower than that of the respective insulating films, since the poly-crystal silicon film 24 is conductive, it is necessary to change the poly-crystal silicon film 24 to the insulating film of silicon oxide film by oxidation treatment.
However, if the above-mentioned oxidation treatment is not sufficient, the following problems arise: in FIGS. 1B to 1E, when the contact hole 25 is being opened, the etching is stopped at the poly-crystal silicon film 24 of slow etching rate, with the result that the contact hole cannot be opened; the semiconductor substrate as the underlayer is not exposed; or even if the contact hole is opened, the contact holes are shorted to each other through the residual poly-crystal silicon film. In addition, the poly-crystal silicon film must be usually heat treated at a high temperature for some hours within an oxidation atmosphere for oxidation. However, since the manufacturing process of the semiconductor device has been treated at lower temperature more and more due to the advance of element microminiaturization, it has become difficult to oxidize the poly-crystal silicon film perfectly, and thereby it is difficult to form the gate self-alignment contact structure.